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AI engineer Divyansh Agrawal built 'Qwenputer,' a modified version of Qwen 3.5 4B that has a 32-bit RISC-V CPU compiled directly into 11 additional transformer layers placed ahead of the model's own weights. The CPU uses the model's Gated DeltaNet state as RAM and can execute C and MicroPython code and arithmetic operations without calling any external tools, and has been shown running the game Doom, albeit slowly.
A new effort called the European RISC-V Industrial Computing Initiative (ERICI) has formed to close gaps between existing RVA23 RISC-V boards, such as the Firefly AIBOX-K3 and Milk-V Jupiter2, and the requirements of true industrial computers. Both boards offer RVA23-compliant SpacemiT K3 processors with hypervisor support, but neither currently meets specs like wide-range 24V power, extended temperature tolerance, fieldbus/real-time I/O, DIN-rail mounting, watchdog hardware, industrial certification, or long-term availability.
Anthropic, working with Theorem, reports using its Claude models to generate formal mathematical proofs of security properties for more than 100 real-world open-source software libraries at the RISC-V assembly level. The company says this is the first large-scale attempt to apply AI-driven formal verification to production software at that level, and that Claude uncovered previously undetected bugs in the process.
The OpenBSD project has shipped version 8.0, its 61st release following a semiannual schedule dating to 1996. The update adds support for Intel Arc A-Series graphics cards, expands kernel virtual address space on AMD64 from 4 GB to 512 GB to allow mapping VRAM above 4 GB, and introduces ARM64 hibernation support, a new RPKI-to-router daemon, RISC-V vector extension support, and updates to LibreSSL and OpenSSH, while dropping Loongson architecture support.
OpenBSD 8.0, the 61st release of the security-focused Unix-like OS, has launched with virtualization upgrades supporting up to 64 vCPUs per VM, ARM64 hibernation, and expanded RISC-V support. The release also adds Intel Arc A-Series graphics support via updated DRM drivers, expands the amd64 kernel's virtual address space from 4GB to 512GB, and includes security hardening to pledge, unveil, and executable validation.
At the Microelectronics 26 forum in Sochi, Russian chip designers demonstrated homegrown processors by running classic video games on them. Baikal Electronics showed its BE-U1000 RISC-V microcontroller powering a business-card-sized console and an NES-styled device called Ushka, while Elvis displayed its Hypercom-U Arm-based SoC and MCST showed Elbrus-powered gaming PCs.
Developer TheAlexKid777 demonstrated the OpenLara open-source Tomb Raider engine running on Espressif's ESP32-P4, a sub-$25 dev board with a dual-core 400MHz RISC-V chip. The game renders at 320x240 and is hardware-scaled up to 1,024x600 with stereo audio, all while the board draws only about 1 watt at peak.
A developer released a browser-hosted IDE that supports writing and running assembly programs for four architectures: M68K, MIPS, RISC-V and Z80. The tool includes a virtual screen and terminal, letting programs draw graphics, read mouse and keyboard input, or handle standard text input and output.
A new open-source repository accompanies a technical blog post detailing how to build a rv32ima instruction-set emulator and run a minimal Linux system on it from the ground up. The project includes emulator code, a small set of emulated devices, machine configuration files, and WebAssembly-exposed functions, along with the Linux build configs needed to reproduce the setup.
A developer documented the process of bringing up the Linux kernel on a new platform by writing a lightweight emulator for a RISC-V CPU rather than using real hardware. The emulator, built in roughly 2000 lines of C++ and implementing the RV32IMA instruction set, provides just enough hardware simulation—MMU support, RAM, an SBI interface, a system timer, and a WD8250-based UART—for Linux to boot. The full source is published on GitHub under WerWolv/riscv-emulator.
Fomu is a tiny programmable device that plugs directly into a USB-A port, combining an FPGA chip, four touch pads, and an RGB LED in a compact plastic case. It ships with enough RAM and storage to run Python natively, while also supporting a RISC-V softcore and other softcores like LM32 and OpenRISC, all programmable through a fully open-source toolchain without accounts, NDAs, or heavy installers.
XCENA partnered with Samsung to build the MX1, a CXL 3.2 device that can expand host memory by up to 2TB of DDR5 while also connecting SSDs and performing on-board computation. The chip, made on Samsung's 4nm process, packs 3072 small RISC-V cores organized into 24 independently schedulable subsystems, alongside two Arm Cortex A53 cores for control, and draws about 40W on the chip and 90W for the full board with DIMMs.