← Home · All topics

Systemverilog

2 GoKawiil briefs on this topic

Developer documents building a VGA driver in SystemVerilog

The author recounts building a VGA display driver as part of a college Digital Logic Design Lab, walking through how CRT-based VGA displays work and the HSync/VSync timing signals that control the electron beam. The piece includes interactive simulations and references timing tables from TinyVGA, such as a 25.175 MHz pixel clock for 60Hz refresh.

lukaswerner.com · 2026-10-20

Google open-sources XLS, a high-level synthesis toolchain for hardware design

Google has released XLS, an Apache 2.0-licensed toolchain that converts high-level functional descriptions into synthesizable Verilog and SystemVerilog hardware designs. The tool lets engineers write logic once and run it both as native host software and as generated hardware, with correctness guarantees ensuring the two versions behave identically.

google.github.io · 2026-09-14