Chinese researchers have developed a capacitor-less DRAM-like memory cell that uses two transistors (2T0C) with dual-gate control, built at a 4F² minimum area, reports TrendForce, citing ResearchGate. The new memory cell architecture uses a self-aligned process. It promises to achieve reliable multi-bit storage, fast DRAM-like write times, and extended retention without a discrete storage capacitor, according to its developers. While it's not a DRAM replacement for now, it could become a viable solution for various eDRAM and stacked 3D memory applications.
Sanctions imposed by the U.S. and its allies on China's semiconductor sector greatly limit the capabilities of the People's Republic to produce chips on advanced production nodes, as companies like CXMT, SMIC, and YMTC do not have access to the latest tools. However, curbing pathfinding, research, and development (R&D) in academia is considerably harder (if possible at all), which is why Chinese scientists can conduct world-class research and develop innovative technologies that are on par with the West.
Before we proceed, let's establish some terminology to avoid confusion. In semiconductor memory discussions, 4F², dual-gate 4F², and 4F² 2T0C are often used interchangeably, even though they describe different layers of the design stack. While all three can appear in the same sentence, each answers a fundamentally different question: how dense the cell is, how the transistor is built, and how the bit is stored.
(Image credit: IME CAS)
4F² is a layout and density metric that defines the minimum possible area of a memory cell — four times the square of the process feature size — and says nothing about the internal structure of the cell. A 4F² footprint can host a classic 1T1C DRAM cell, an SRAM bitcell, or even a resistive memory element.
is a layout and density metric that defines the minimum possible area of a memory cell — four times the square of the process feature size — and says nothing about the internal structure of the cell. A 4F² footprint can host a classic 1T1C DRAM cell, an SRAM bitcell, or even a resistive memory element. The term ' dual-gate ' describes a device-level detail: a dual-gate transistor uses two independently controlled gates to improve electrical control over the channel, reduce leakage, and stabilize threshold voltage. Dual-gate transistors are widely used in the semiconductor industry in logic (FinFET is a dual-gate transistor), SRAM, or DRAM-like cells.
' describes a device-level detail: a dual-gate transistor uses two independently controlled gates to improve electrical control over the channel, reduce leakage, and stabilize threshold voltage. Dual-gate transistors are widely used in the semiconductor industry in logic (FinFET is a dual-gate transistor), SRAM, or DRAM-like cells. Finally, 4F² 2T0C describes the actual memory architecture featuring two transistors that store data without a dedicated capacitor by relying instead on charge retained in a transistor channel or floating node. This design gives the cell DRAM-like behavior: it still needs refresh, but avoids the scaling challenges associated with deep capacitors.
When combined, the phrase 'dual-gate 4F² 2T0C memory' means a capacitor-less DRAM cell, based on dual-gate transistors, with DRAM-class density at a minimum. In short, we are dealing with three separate concepts combined in a unique design, rather than a singular invention.
4F² dual-gate 2T0C memory
Being unconstrained by curbs set by the U.S. and allies, National Key Laboratory of Integrated Circuit Manufacturing Technology at the Institute of Microelectronics of Chinese Academy of Sciences (IME CAS) teamed up with the Beijing Superstring Academy of Memory Technology (SAMT), and Shandong University to develop a 4F² 2T0C memory cell architecture that can store two bits of data per-cell (4 levels of charge), offering a write latency of around 50ns, and data retention for up to 470 seconds, making it a viable memory technology. However, while this isn't a DRAM killer, it may be a potent candidate for embedded DRAM and stacked 3D memory built on top of logic.
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