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IBM's next-gen AI processor is the first time it has supported dual ISA execution natively within the same core. Born out of a collaboration between IBM and Arm that was announced in April, the chip is designed to bring the software support available across the Arm ecosystem to IBM's mainframes, allowing businesses to unify deployment rather than relying on separate Arm/x86 servers and z/Architecture mainframes for different purposes.
The approach here isn't a heterogeneous CPU with separate Arm cores packaged on the same chip; IBM has built a core that can execute either z/Architecture or AArch64 instructions, and can switch between them dynamically "within nanoseconds," according to the company. During the Hot Chips 2026 reveal, IBM says it believes this is the first processor to treat both ISAs as "first-class citizens."
IBM relies on Linux Kernel-level Virtual Machine (KVM) to support AArch64 instructions, the same mechanism that allows IBM to support Linux on Z mainframes. Standard z/Architecture instructions bypass KVM. The idea is to ensure that mainframe reliability isn't sacrificed for broader software support, with IBM claiming 99.999999% uptime, even further than traditional high-availability claims. IBM says that equates to just 0.032 seconds of downtime per year.
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Much of the development in the software world, particularly around AI, happens with x86 and/or Arm targets in mind, leaving the mainframe behind to figure out its own solution. IBM could, and has, worked to port this software to s390x, but that's not a long-term solution. "We would never be able to work with all of them," Tina Tarquinio, chief product officer at IBM for IBM Z and LinuxONE, told VentureBeat. IBM's dual-ISA core can execute Arm software without modifications, according to the company, allowing Arm-based virtual machines to run as if they were operating on native-Arm silicon. And that's because, well, they are operating on native-Arm silicon, just in a different way.
A high-level look at IBM's dual-ISA processor and next-gen Spyre accelerator
The processor that presumably will live in z18 mainframes comes with 11 high-performance cores, built on a 2nm process, that can operate at a base frequency of 5.7 GHz. Even on those specs, and ignoring dual-ISA execution, it's a considerable step up over the current Telum II processor that IBM introduced in 2024. That chip features eight cores operating at up to 5.5 GHz. Otherwise, IBM's dual-ISA processor comes with the same 36 MB of private L2, as well as virtual L3 and L4. These caches are larger than Telum II at 432 MB of virtual L3 and 3.5 GB of virtual L4.
Also carried forward is an on-chip DPU, as well as hardware accelerators for AI, compression, and cryptography workloads, same as Telum II. Outside of more cores and higher clocks, much of the work on IBM's dual-ISA processor happened, naturally, in the core itself, which we'll dig into in the next section.
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