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D-Matrix introduced Raptor, a new accelerator that stacks compute logic directly on top of DRAM dies to tackle memory bottlenecks in generative AI inference. The design aims to bridge the gap between SRAM's speed but tiny capacity and HBM's larger capacity but bandwidth and power limitations, following the company's earlier Corsair and JetStream products.
Samsung presented its Processing-in-Memory approach for LPDDR5X-9600 chips, embedding a MAC computation block into each of the 16 DRAM banks while keeping compatibility with standard memory controllers. By computing directly within each bank, the design taps into 614 GB/s of internal bandwidth versus the 76.8 GB/s ceiling of conventional two-bank DRAM access. Each PIM block includes an instruction register file, a source register file for activation vectors, and a scale register, with model weights fetched directly from the attached DRAM bank.
At Hot Chips 2026, Cerebras detailed its next two wafer-scale accelerator generations, including a new Nexus rack architecture for the CS-4 system that triples rack-scale performance using three WS-3T engines. The company also confirmed that its future CS-6 system will introduce 3D-stacked DRAM directly on top of its wafer-scale logic and SRAM, marking a first for its chip design.
OpenAI has revealed details of Jalapeño, a custom inference chip developed with Broadcom over roughly 16 months, at the Hot Chips conference. SemiAnalysis tested the chip using its InferenceX benchmark suite and found it outperforms Nvidia, AMD, and Google chips across multiple open-source models, despite being OpenAI's first hardware effort.
At Hot Chips 2026, Intel disclosed full specifications for its Crescent Island AI accelerator, including 32 Xe3P cores, 256 XMX engines, 32MB of L2 cache, PCIe Gen5 x16, and a 350W TDP. Shipping units will carry 160GB of LPDDR5X memory, though ODM designs can scale up to 480GB of VRAM.
At Hot Chips 2026, IBM unveiled an early look at a future mainframe processor featuring 11 IBM Z cores on a 2-nanometer process, clocked above 5.7 GHz, capable of natively executing both z/Architecture and AArch64 instructions on the same cores without emulation. The chip will include specialized accelerators for AI fraud detection, I/O, compression, cryptography and sorting, plus a large cache hierarchy topping out near 3.5 GB of virtual L4 cache. IBM hasn't named the chip or its host system but expects it around 2028, likely powering a future z18-class mainframe.
At Hot Chips 2026, SK hynix's Jaesik Lee said hybrid bonding won't be ready in time for HBM4E and will instead debut with HBM5, as current HBM4 packages are already constrained by a 775-micron thickness ceiling matching standard logic wafers. To keep scaling within that limit, 16-Hi HBM4 stacks now use dies thinned to about 50 microns with half the interlayer gap of 12-Hi designs, while SK hynix continues using its existing MR-MUF bonding method through upcoming Nvidia Rubin-generation products.
At Hot Chips 2026, IBM revealed a next-generation processor built on a 2nm node with 11 cores, each running at a 5.7 GHz base clock. The chip's key innovation is a core that can natively execute both z/Architecture and AArch64 instructions, switching between them within nanoseconds, a result of IBM's April partnership with Arm.
Nvidia is working to extend CUDA compatibility beyond x86-64 and aarch64 to RISC-V CPUs, according to a Hot Chips 2026 presentation. The company laid out strict hardware requirements, including RVA23 compliance, adherence to RISC-V server SoC and platform specs, ACPI support, and PCIe coherency, to ensure CUDA runs efficiently rather than falling back on lowest-common-denominator code.
IBM unveiled a new mainframe processor at Hot Chips that will power future IBM Z and LinuxONE systems, marking the first chip whose cores can execute both IBM's proprietary instruction set and Arm's, switching between them in nanoseconds. Each of the chip's 11 cores is built to be dual-architecture rather than pairing separate Arm and Z cores side by side, letting Arm-native Linux and AI software run alongside traditional z/OS transaction workloads on the same silicon.