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Chip-puzzle contest reveals mystery ASIC was a Star Battle solver checker

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GoKawiil Brief

A chip-design puzzle published in August challenged readers to reverse-engineer a small chip's function from only its raw GDS layout, with no netlist or signal names provided. The organizers have now revealed the chip validates solutions to an 11x11 'Two Not Touch' Star Battle puzzle, using row, column and region counters plus a delay line to prevent adjacent stars, and an LFSR-obfuscated ROM to reveal the solution text once all checks pass.

Why It Matters

GoKawiil's interpretation of the reporting above, not reported fact.

The roughly 400 submissions from over 30 countries, using tools like KLayout, Yosys and Z3 alongside custom-built analyzers, suggest a broad and technically diverse community interested in hardware reverse engineering as a hobby or skill-building exercise. The variety of approaches, including some entrants attacking the LFSR obfuscation directly, indicates that puzzles like this can surface creative analysis techniques that might inform both security research and chip-design education.

Key Takeaways
Worth a Look

FPGA Development Board Kit — If you enjoyed reverse-engineering this ASIC's GDS layout, an FPGA board lets you design and test your own digital logic puzzles and checkers hands-on. It's a perfect way to experiment with Yosys and other open-source toolchains mentioned in the article. Great for hobbyists wanting to go from chip-reading to chip-building.

See FPGA Development Board Kit on Amazon → Affiliate link — we may earn a commission on purchases, at no extra cost to you. Product picked by AI based on this article; it is not a tested recommendation.

Source: blog.janestreet.com, 2026-10-02

Published there as: “Results from the ASIC puzzle”

Read the original report → The summary and analysis above are GoKawiil's own, written from reporting by the source above. Facts and quotes belong to the original publisher.