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Chip-puzzle contest reveals mystery ASIC was a Star Battle solver checker

A chip-design puzzle published in August challenged readers to reverse-engineer a small chip's function from only its raw GDS layout, with no netlist or signal names provided. The organizers have now revealed the chip validates solutions to an 11x11 'Two Not Touch' Star Battle puzzle, using row, column and region counters plus a delay line to prevent adjacent stars, and an LFSR-obfuscated ROM to reveal the solution text once all checks pass.

Jane Street's ASIC reverse-engineering puzzle solved via GDS layout analysis

Jane Street released a puzzle challenging participants to reverse engineer an ASIC chip from just two files: a GDS layout file and a VCD file with example inputs and outputs. Kjartan van Driel and Leander Post worked through the challenge, breaking down how the chip's physical layout, organized into layers and reusable cells representing logic gates, could be decoded to understand its function without access to the original Verilog design.