GoKawiilJane Street's ASIC reverse-engineering puzzle solved via GDS layout analysis
Jane Street released a puzzle challenging participants to reverse engineer an ASIC chip from just two files: a GDS layout file and a VCD file with example inputs and outputs. Kjartan van Driel and Leander Post worked through the challenge, breaking down how the chip's physical layout, organized into layers and reusable cells representing logic gates, could be decoded to understand its function without access to the original Verilog design.
GoKawiil's interpretation of the reporting above, not reported fact.
This kind of exercise mirrors real-world hardware security and IP theft concerns, where engineers must infer a chip's logic purely from its physical structure. It also serves as an accessible teaching tool for understanding how abstract circuit designs get translated into physical silicon layouts, bridging a gap between software and hardware engineering skillsets.
- The puzzle provided only a GDS layout file and a VCD example input/output file, with no original design source.
- GDS files organize chip layouts into layers and hierarchical cells representing logic gates, offering structural clues despite lacking Verilog-level detail.
- The write-up is framed as a full solution guide for those who didn't have time to complete Jane Street's original challenge.
No Starch Press "The Hardware Hacking Handbook — If puzzling out an ASIC's gates from a GDS layout sounds like your idea of fun, this book walks through how embedded hardware is probed, analyzed, and broken open. It's a great companion for readers who want to go from reading someone else's reverse-engineering write-up to attempting their own.
See No Starch Press "The Hardware Hacking Handbook on Amazon → Affiliate link — we may earn a commission on purchases, at no extra cost to you. Product picked by AI based on this article; it is not a tested recommendation.Source: kjartanvandriel.github.io, 2026-09-07
Published there as: “Reverse Engineering an ASIC”
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