GoKawiil
Tech News
Zettascale, a YC S24 startup, is recruiting ASIC and FPGA engineers to design custom chips aimed at advancing artificial superintelligence hardware. The company's careers page invites applicants without a specific listed role to send a demo of prior work to its hiring email for consideration.
Jane Street released a puzzle challenging participants to reverse engineer an ASIC chip from just two files: a GDS layout file and a VCD file with example inputs and outputs. Kjartan van Driel and Leander Post worked through the challenge, breaking down how the chip's physical layout, organized into layers and reusable cells representing logic gates, could be decoded to understand its function without access to the original Verilog design.
A blogger with an engineering background details how they spent about a month reverse-engineering an ASIC chip design as part of a public puzzle set by trading firm Jane Street. The challenge involved analyzing a GDS chip-layout file to determine the chip's function, first through an easier warmup version with more design information, then a harder unaided version. The author has published their code on GitHub and plans follow-up posts explaining each technical step in more depth.
Waymo disclosed it built a proprietary 5-nanometer ASIC chip that pre-processes the massive stream of sensor data—including feeds from 13 cameras—before it reaches its self-driving system's core computer. The company says the chip delivers more than 1,000 TOPS of processing power, putting it near the performance level of Nvidia's DRIVE AGX Thor chip, and is a key part of the vehicle now rolling out to all riders in Los Angeles, Phoenix and San Francisco.