GoKawiilOpenAI says AI-assisted design cut Jalapeño chip's RTL-to-tapeout time to nine months
OpenAI head of hardware Richard Ho said the company's Jalapeño ASIC went from initial RTL design to tapeout in roughly nine months, with total concept-to-reveal time under two years. Ho said the chip was built from scratch using OpenAI's own internal AI models, including its Codex coding platform, alongside standard EDA tools, and that other engineering teams have been asking how OpenAI achieved the pace.
GoKawiil's interpretation of the reporting above, not reported fact.
Ho frames the nine-month timeline as a new industry baseline, replacing the traditional 18-month-to-two-year cycle even when legacy IP exists, which could pressure other chipmakers to adopt similar AI-assisted workflows. Because OpenAI used its own proprietary models rather than commercial EDA AI tools from Cadence or Synopsys, the claim also implicitly promotes OpenAI's own AI products as engineering tools, a framing that invites scrutiny given the company's commercial interest in Codex adoption.
- OpenAI's Jalapeño ASIC reportedly moved from RTL to tapeout in about nine months, concept to reveal in under two years.
- OpenAI used its own internal AI models, including Codex, alongside existing EDA tools, building the design from scratch.
- Head of hardware Richard Ho says this establishes a new industry baseline and other companies are asking how it was done.
Source: tomshardware.com — Jake Roach, 2026-09-30
Published there as: “‘This is how AI should be used’ — OpenAI head of hardware breaks down the AI-assisted design of its Jalapeño ASIC”
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