Tom's Hardware Premium is extending free access to its AI Chip Design Week series until Monday, October 5. The coverage includes an unredacted interview with OpenAI hardware VP Richard Ho about the Broadcom-co-developed Jalapeño inference chip, primers on AI's role in chip design, vendor tool breakdowns including Synopsys' new 'Autopilot' platform for AgentEngineer, and a report on IP security risks featuring academics Domenec Forte and Simon Moore.
tomshardware.com
· 2026-10-03
OpenAI is deploying its new Jalapeño AI chip in racks alongside AMD's EPYC Turin CPUs, each configured with 1.5TB of memory, rather than Nvidia's newer Vera processor. Richard Ho, OpenAI's VP and Head of Hardware, told Tom's Hardware that Turin was chosen for pragmatic reasons, calling Vera 'a little bit behind' in maturity and noting partners already had experience with AMD's chip.
tomshardware.com
· 2026-10-02
OpenAI head of hardware Richard Ho said the company's Jalapeño ASIC went from initial RTL design to tapeout in roughly nine months, with total concept-to-reveal time under two years. Ho said the chip was built from scratch using OpenAI's own internal AI models, including its Codex coding platform, alongside standard EDA tools, and that other engineering teams have been asking how OpenAI achieved the pace.
tomshardware.com
· 2026-09-30
OpenAI's Head of Hardware Richard Ho told Tom's Hardware that the company's new Jalapeño inference ASIC, developed with Broadcom, is designed primarily to meet OpenAI's own growing compute demand. Ho said the chip 'could' be used by others eventually, but that satisfying OpenAI's internal needs remains the priority for the foreseeable future. At Hot Chips 2026, OpenAI shared benchmarks showing Jalapeño running GPT-OSS, DeepSeek R1 and Kimi K2.5 against Nvidia's GB200 and GB300 accelerators.
tomshardware.com
· 2026-09-28
OpenAI's VP of Hardware, Richard Ho, spoke with Tom's Hardware following the August 2026 Hot Chips reveal of the company's Jalapeño inference ASIC. Ho said the chip's development leaned heavily on AI tools to compress the design timeline, and that efficiency, not raw performance, was the primary driver behind building custom silicon.
tomshardware.com
· 2026-09-28
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