A chip-design puzzle published in August challenged readers to reverse-engineer a small chip's function from only its raw GDS layout, with no netlist or signal names provided. The organizers have now revealed the chip validates solutions to an 11x11 'Two Not Touch' Star Battle puzzle, using row, column and region counters plus a delay line to prevent adjacent stars, and an LFSR-obfuscated ROM to reveal the solution text once all checks pass.
blog.janestreet.com
· 2026-10-02
Jane Street released a puzzle challenging participants to reverse engineer an ASIC chip from just two files: a GDS layout file and a VCD file with example inputs and outputs. Kjartan van Driel and Leander Post worked through the challenge, breaking down how the chip's physical layout, organized into layers and reusable cells representing logic gates, could be decoded to understand its function without access to the original Verilog design.
kjartanvandriel.github.io
· 2026-09-07
A blogger with an engineering background details how they spent about a month reverse-engineering an ASIC chip design as part of a public puzzle set by trading firm Jane Street. The challenge involved analyzing a GDS chip-layout file to determine the chip's function, first through an easier warmup version with more design information, then a harder unaided version. The author has published their code on GitHub and plans follow-up posts explaining each technical step in more depth.
jestoph.com
· 2026-09-04
GoKawiil