GoKawiilDeveloper publishes vectorized CLZ/CTZ bit-counting technique using floating-point tricks
A developer building an FPU emulator devised a way to compute leading-zero and trailing-zero bit counts using floating-point exponent manipulation instead of native CLZ/CTZ CPU instructions, and found the approach can be vectorized across multiple integers at once using SIMD (u64x4). Benchmarks on the author's Haswell CPU showed the vectorized version running at 0.45 ns per iteration versus 1 ns for scalar code, with a separate test on Alder Lake by Ian Qvist showing 0.29 ns versus 0.85 ns.
GoKawiil's interpretation of the reporting above, not reported fact.
Native CLZ/CTZ instructions can have surprisingly high latency on modern CPUs (the piece cites 3 cycles for tzcnt on Arrow Lake), so a vectorized software alternative could speed up workloads like emulators, compression, or bit-manipulation-heavy code that process many integers at once. Because the method relies on 64-bit double-precision mantissas, it appears limited to 32-bit inputs, which may constrain where it can be applied without further work.
- A floating-point exponent trick can replace hardware CLZ/CTZ instructions for 32-bit integers.
- The technique can be vectorized across four 64-bit lanes using AVX-style SIMD instructions.
- Benchmarks on Haswell and Alder Lake CPUs show roughly 2-3x speedups over scalar implementations.
Source: purplesyringa.moe, 2026-10-11
Published there as: “Vectorized CLZ and CTZ”
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