GoKawiilDeveloper publishes vectorized CLZ/CTZ bit-counting technique using floating-point tricks
A developer building an FPU emulator devised a way to compute leading-zero and trailing-zero bit counts using floating-point exponent manipulation instead of native CLZ/CTZ CPU instructions, and found the approach can be vectorized across multiple integers at once using SIMD (u64x4). Benchmarks on the author's Haswell CPU showed the vectorized version running at 0.45 ns per iteration versus 1 ns for scalar code, with a separate test on Alder Lake by Ian Qvist showing 0.29 ns versus 0.85 ns.