GoKawiilIntel details future roadmap for EMIB and Foveros chip packaging technologies
Intel's advanced packaging methods, EMIB and Foveros, now underpin most of its client and data center CPUs after debuting with 2017's Kaby Lake-G chips. The company's roadmap shows the two technologies evolving to be both more sophisticated for high-end products and simplified for cost-sensitive ones, while increasingly working together alongside new process nodes. Intel's stated long-term goal is building system-in-package designs as large as 12 reticles combining EMIB with Foveros Direct 3D.
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The convergence of EMIB and Foveros suggests Intel views chiplet-based packaging, rather than monolithic die shrinks alone, as its primary path to sustained performance gains, a strategy it adopted after struggles with 10nm manufacturing. Scaling to 12-reticle packages could let Intel compete more aggressively against rivals like AMD and TSMC-based designs in both PC and data center markets, though execution risk remains given Intel's acknowledged mixed track record with prior chiplet projects.
- EMIB and Foveros now appear in most of Intel's modern CPU and GPU products.
- The two packaging technologies are becoming more integrated with each other and with new process nodes.
- Intel aims to eventually build system-in-packages as large as 12 reticles using combined EMIB and Foveros Direct 3D.
Source: tomshardware.com — Anton Shilov, 2026-10-14
Published there as: “Analyzing Intel's EMIB and Foveros advanced packaging roadmaps”
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