GoKawiilAMD's Zen 6 EPYC 'Venice' chips tested ahead of launch, show major gains over Zen 5
AMD's upcoming EPYC 'Venice' server processors, the first to use the Zen 6 architecture, have been benchmarked ahead of release. Built on TSMC's N2P node, Zen 6 introduces a redesigned vector engine with native FP16 support, split integer schedulers, dual I/O dies enabling 16 memory channels, and larger core-dense CCDs scaling up to 32 cores with quadrupled L3 cache. In testing, a 256-core, 1,024-thread EPYC 9996 outperformed the previous-generation 768-thread EPYC 9965 by 93% in SPEC CPU 2026 benchmarks.
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The architectural overhaul suggests AMD is pushing nearly every available lever—core density, cache, memory bandwidth, and vector throughput—to widen its lead over rivals like Nvidia's Vera platform in data-center workloads. These server-chip advances also hint at what AMD's consumer-focused 'Olympic Ridge' Zen 6 chips, expected next year, might inherit in terms of performance and efficiency gains.
- Zen 6 EPYC 'Venice' chips use TSMC's N2P node with a redesigned vector engine and native FP16 support.
- New dual I/O die design enables 16 memory channels but reduces PCIe 6.0 lanes versus the prior SP8 platform.
- A 256-core EPYC 9996 showed a 93% performance gain over the previous-gen EPYC 9965 in SPEC CPU 2026 testing.
Source: tomshardware.com — Jake Roach, 2026-11-10
Published there as: “AMD Zen 6 EPYC ‘Venice’ deep dive and benchmarking”
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