GoKawiil
Tech News
A technical deep dive explains why translating x86 software to run on ARM chips runs into a persistent obstacle: x86's strict Total Store Ordering (TSO) memory model clashes with ARM's much more relaxed memory consistency rules. The piece walks through why this mismatch affects essentially every emulated multi-threaded application and outlines the various workarounds engineers use, noting some cases where no clean fix exists.
At Hot Chips 2026, IBM unveiled an early look at a future mainframe processor featuring 11 IBM Z cores on a 2-nanometer process, clocked above 5.7 GHz, capable of natively executing both z/Architecture and AArch64 instructions on the same cores without emulation. The chip will include specialized accelerators for AI fraud detection, I/O, compression, cryptography and sorting, plus a large cache hierarchy topping out near 3.5 GB of virtual L4 cache. IBM hasn't named the chip or its host system but expects it around 2028, likely powering a future z18-class mainframe.