Arm Instruction Set

IBM unveils dual-ISA mainframe core supporting z/Architecture and Arm at Hot Chips 2026

IBM's next-generation mainframe processor, discussed by Christian Jacobi and Christian Zoellin at Hot Chips 2026, integrates decoders capable of handling both the z/Architecture instruction set and Arm instructions within the same core. The chip uses a shared decode pipeline with separate instruction decoders for the two architectures, a design approach IBM says differs from earlier dual-ISA attempts like Itanium.

chipsandcheese.com · 2026-08-31

IBM debuts mainframe chip whose cores natively run both Arm and Z instructions

IBM unveiled a new mainframe processor at Hot Chips that will power future IBM Z and LinuxONE systems, marking the first chip whose cores can execute both IBM's proprietary instruction set and Arm's, switching between them in nanoseconds. Each of the chip's 11 cores is built to be dual-architecture rather than pairing separate Arm and Z cores side by side, letting Arm-native Linux and AI software run alongside traditional z/OS transaction workloads on the same silicon.

venturebeat.com · 2026-08-24