At Hot Chips 2026, IBM unveiled an early look at a future mainframe processor featuring 11 IBM Z cores on a 2-nanometer process, clocked above 5.7 GHz, capable of natively executing both z/Architecture and AArch64 instructions on the same cores without emulation. The chip will include specialized accelerators for AI fraud detection, I/O, compression, cryptography and sorting, plus a large cache hierarchy topping out near 3.5 GB of virtual L4 cache. IBM hasn't named the chip or its host system but expects it around 2028, likely powering a future z18-class mainframe.
techspot.com
· 2026-08-25
At Hot Chips 2026, SK hynix's Jaesik Lee said hybrid bonding won't be ready in time for HBM4E and will instead debut with HBM5, as current HBM4 packages are already constrained by a 775-micron thickness ceiling matching standard logic wafers. To keep scaling within that limit, 16-Hi HBM4 stacks now use dies thinned to about 50 microns with half the interlayer gap of 12-Hi designs, while SK hynix continues using its existing MR-MUF bonding method through upcoming Nvidia Rubin-generation products.
tomshardware.com
· 2026-08-24
At Hot Chips 2026, IBM revealed a next-generation processor built on a 2nm node with 11 cores, each running at a 5.7 GHz base clock. The chip's key innovation is a core that can natively execute both z/Architecture and AArch64 instructions, switching between them within nanoseconds, a result of IBM's April partnership with Arm.
tomshardware.com
· 2026-08-24
Nvidia is working to extend CUDA compatibility beyond x86-64 and aarch64 to RISC-V CPUs, according to a Hot Chips 2026 presentation. The company laid out strict hardware requirements, including RVA23 compliance, adherence to RISC-V server SoC and platform specs, ACPI support, and PCIe coherency, to ensure CUDA runs efficiently rather than falling back on lowest-common-denominator code.
chipsandcheese.com
· 2026-08-24
IBM unveiled a new mainframe processor at Hot Chips that will power future IBM Z and LinuxONE systems, marking the first chip whose cores can execute both IBM's proprietary instruction set and Arm's, switching between them in nanoseconds. Each of the chip's 11 cores is built to be dual-architecture rather than pairing separate Arm and Z cores side by side, letting Arm-native Linux and AI software run alongside traditional z/OS transaction workloads on the same silicon.
venturebeat.com
· 2026-08-24
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