GoKawiilIBM unveils dual-ISA mainframe core supporting z/Architecture and Arm at Hot Chips 2026
IBM's next-generation mainframe processor, discussed by Christian Jacobi and Christian Zoellin at Hot Chips 2026, integrates decoders capable of handling both the z/Architecture instruction set and Arm instructions within the same core. The chip uses a shared decode pipeline with separate instruction decoders for the two architectures, a design approach IBM says differs from earlier dual-ISA attempts like Itanium.