GoKawiilLiteDRAM docs detail DDR3+ interface tuning and PHY signal mapping
A LiteDRAM documentation chapter breaks down the command/address and data signal paths between an FPGA and DRAM, listing signals such as CK, CS#, DQ, DQS and DM and explaining how each byte lane is routed and timed independently. It also describes how LiteDRAM's platform file maps DRAM pads to these signals and how helper functions PHYPadsReducer and PHYPadsCombiner reshape pad groups for different lane counts or chip configurations.