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AMD Zen 6 engineering sample with 24GB LPDDR5 memory surfaces in benchmarks

An AMD engineering sample bearing part number 100-000001930-12_Y has appeared on OpenBenchmarking, featuring a six-core, 12-thread CPU and 24GB of LPDDR5 memory running at 9,600 MT/s across four SK Hynix packages. The chip's microcode revision reportedly falls within AMD's range for Zen 6 processors, and reports from TechPowerUp and Notebookcheck link it to AMD's rumored Gainsborough chip family.

Hobbyist rebuilds laptop DDR5 SODIMMs into desktop memory modules

Electronics hobbyist Blighted Agent bought a 2x16GB SK hynix DDR5-5600 SODIMM kit for $120 and transferred its memory chips onto blank desktop DDR5 PCBs bought from AliExpress, creating a working 2x16GB DDR5-7800 desktop kit. Total parts cost came to about $175, including PCBs, heatsinks, and reballing materials, with the process involving desoldering the chips with hot air, reballing them, and remounting them onto the new boards along with the SPD and BIOS chips.

Windows 11 still contains EmulateHeap, a Windows 95 memory-manager compatibility shim

Windows 11 26H2 retains a compatibility fix called EmulateHeap that reproduces Windows 95's forgiving memory-management behavior for older applications that depend on it. The feature traces back to a 1990s bug in SimCity, where Microsoft rewrote part of Windows 95's memory allocator to stop the game crashing rather than wait for a patch, and later generalized that fix into EmulateHeap to keep other legacy apps running on newer Windows versions.

Stealthium demonstrates runtime detection of in-memory AI model weight tampering

Stealthium published research on Rank-One Model Editing (ROME) attacks, a technique where malicious Python code alters a model's weights directly in GPU memory without touching disk files. The company ran a ROME attack in its lab and showed its runtime sensor catching the tampering by linking CUDA kernel launches to the Python code that triggered them, alongside ongoing work to trace weight changes back to their originating call stack.

Speculative decoding speeds LLMs by shifting GPU work, not reducing it

A technical explainer argues that speculative decoding does not make large language model inference faster by cutting the number of floating-point operations performed. In fact, total compute (FLOPs) for a given sequence increases under the technique, since a small draft model proposes tokens that a larger model must then verify in a single parallel forward pass.

CXMT shares drop 7.8% despite forecasting $19.6 billion profit swing

Chinese memory chipmaker CXMT saw its shares close 7.8% lower Monday despite forecasting net profit of 131-132.5 billion yuan ($19.58 billion) for the first nine months of 2026, reversing a 5.28 billion yuan loss a year earlier. The company also projected revenue of roughly 265-270 billion yuan, a jump of over 230 billion yuan from the same period last year, according to a regulatory filing.

Technical essay models transformer layers as memory stores with measurable recall capacity

A technical blog post argues that linear layers, MLPs, and self-attention can each be understood as a type of memory store that holds key-value pairs and retrieves them later. The author introduces an 'interference-to-signal ratio' to measure how well each layer type recalls stored information as the number of memories grows, estimating capacities of roughly 64 memories for linear layers, 2,700 for MLPs, and over a million for self-attention with 64-dimensional keys.

Memory price spikes push phone costs up 20%, battery swaps stay pricey

Rising memory chip costs have driven an estimated 20 percent increase in smartphone prices this year, prompting consumers to keep devices longer or buy refurbished units. Despite this shift toward longer phone lifespans, companies like Apple and Samsung continue charging $89 to $229 for out-of-warranty battery replacements, with extended warranty plans being the main way to get cheaper service.

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