GoKawiilSamsung explores moving memory controller onto HBM base die to curb power growth
Samsung presented plans at Hot Chips 2026 to rethink High Bandwidth Memory design by fabricating the base die on a 4nm logic process instead of a DRAM node, starting with HBM4 and HBM4E. This logic-node shift reduces power consumption and frees up unused base die area, which Samsung is now exploring ways to use, including a first phase that would integrate the memory controller directly onto the base die.
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As HBM generations pack more bandwidth, the interface between the base die and host chip is becoming a bottleneck for both area and power, threatening the efficiency gains needed for AI and high-performance computing workloads. By repurposing the base die with logic-grade fabrication, Samsung could unlock architectural changes that shift traditional DRAM-management tasks closer to memory, potentially reshaping how future accelerators interact with HBM.
- Samsung moved HBM4/HBM4E base die fabrication to a 4nm logic process instead of a DRAM node.
- The switch reduces power draw and leaves extra unused area on the base die.
- Samsung is considering integrating the memory controller onto the base die as an early optimization phase.
Computer Architecture: A Quantitative Approach (Hennessy & Patterson) — If deep dives into HBM base dies, TSVs and interposers are your idea of a good time, this is the classic text that explains the memory-hierarchy and bandwidth trade-offs behind it all. Hennessy and Patterson walk through how bandwidth, power and area constraints shape real chip design, giving great context for Hot Chips talks like Samsung's.
See Computer Architecture: A Quantitative Approach (Hennessy & Patterson) on Amazon → Affiliate link — we may earn a commission on purchases, at no extra cost to you. Product picked by AI based on this article; it is not a tested recommendation.Source: chipsandcheese.com — Chester Lam, 2026-08-24
Published there as: “Hot Chips 2026: Samsung and HBM Base Die Opportunities”
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