GoKawiilIMECAS demonstrates working GAA transistors using DUV lithography, no EUV
China's Institute of Microelectronics (IMECAS) says it has completed early process integration for stacked-nanosheet gate-all-around transistors built entirely with immersion DUV lithography, avoiding EUV tools that Chinese fabs cannot access. The devices reportedly achieved Ion/Ioff ratios above the 5×10⁵ threshold needed to prove effective gate control over the nanosheet stack. However, IMECAS has not released key figures like gate pitch, transistor density, or nanosheet dimensions needed to compare it to actual 3nm-class chips from TSMC or Samsung.
GoKawiil's interpretation of the reporting above, not reported fact.
This shows Chinese researchers can produce working GAA transistor structures despite export restrictions on EUV lithography machines, proving a technical pathway exists even if it's far from commercial-scale manufacturing. It signals China's semiconductor sector is pursuing an independent route to advanced nodes rather than being fully blocked by sanctions, though the gap to mass-produced leading-edge chips remains substantial.
- IMECAS built functional GAA transistors using only DUV, not EUV, lithography.
- Test results show working gate control but no data on density or dimensions comparable to 3nm chips.
- The result is an early research milestone, not a proven manufacturable 3nm process.
Source: tomshardware.com — Anton Shilov, 2026-09-21
Published there as: “China crafts working 3nm gate-all-around transistors without EUV — stacked nanosheets target 3nm without EUV, but full node remains distant”
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