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3nm Process

1 GoKawiil brief on this topic

IMECAS demonstrates working GAA transistors using DUV lithography, no EUV

China's Institute of Microelectronics (IMECAS) says it has completed early process integration for stacked-nanosheet gate-all-around transistors built entirely with immersion DUV lithography, avoiding EUV tools that Chinese fabs cannot access. The devices reportedly achieved Ion/Ioff ratios above the 5×10⁵ threshold needed to prove effective gate control over the nanosheet stack. However, IMECAS has not released key figures like gate pitch, transistor density, or nanosheet dimensions needed to compare it to actual 3nm-class chips from TSMC or Samsung.