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openTPU: open-source AI accelerator designed by AI agents runs on real FPGA hardware

read original get Xilinx Kintex-7 FPGA Development Board → more articles
GoKawiil Brief

A project called openTPU has released an open-source AI inference accelerator whose hardware design, instruction set, compiler and simulator were developed by AI agents rather than human engineers. The design was tested on an Inspur YPCB-00338 FPGA card, successfully running ten language models including LFM2.5, Qwen3, Gemma 4 and SmolLM3, with output matching the simulator bit-for-bit.

Why It Matters

GoKawiil's interpretation of the reporting above, not reported fact.

The project frames itself as a test of how far AI agents can go in hardware design, including building a chip capable of running inference for AI models themselves, which could hint at future self-reinforcing loops in AI development tooling. Because the entire codebase, from SystemVerilog to the compiler, is published as a learning resource, it may lower the barrier for others to understand or experiment with custom accelerator design. The modest performance figures, several models run at single-digit to double-digit tokens per second, suggest this is a proof-of-concept rather than a commercially competitive chip.

Key Takeaways
Worth a Look

Xilinx Kintex-7 FPGA Development Board — If you're intrigued by openTPU's approach to building AI accelerators from scratch, a Kintex-7 FPGA dev board lets you experiment with the same class of hardware used in the project. It's a great way to get hands-on with SystemVerilog design, custom instruction sets, and real PCIe-driven inference like the openTPU team did.

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Source: github.com, 2026-10-06

Published there as: “AI is now capable of developing its own inference hardware”

Read the original report → The summary and analysis above are GoKawiil's own, written from reporting by the source above. Facts and quotes belong to the original publisher.