GoKawiil
Tech News
D-Matrix introduced Raptor, a new accelerator that stacks compute logic directly on top of DRAM dies to tackle memory bottlenecks in generative AI inference. The design aims to bridge the gap between SRAM's speed but tiny capacity and HBM's larger capacity but bandwidth and power limitations, following the company's earlier Corsair and JetStream products.
At Hot Chips 2026, Cerebras detailed its next two wafer-scale accelerator generations, including a new Nexus rack architecture for the CS-4 system that triples rack-scale performance using three WS-3T engines. The company also confirmed that its future CS-6 system will introduce 3D-stacked DRAM directly on top of its wafer-scale logic and SRAM, marking a first for its chip design.
At Hot Chips 2026, Intel disclosed full specifications for its Crescent Island AI accelerator, including 32 Xe3P cores, 256 XMX engines, 32MB of L2 cache, PCIe Gen5 x16, and a 350W TDP. Shipping units will carry 160GB of LPDDR5X memory, though ODM designs can scale up to 480GB of VRAM.
At Hot Chips 2026, IBM unveiled an early look at a future mainframe processor featuring 11 IBM Z cores on a 2-nanometer process, clocked above 5.7 GHz, capable of natively executing both z/Architecture and AArch64 instructions on the same cores without emulation. The chip will include specialized accelerators for AI fraud detection, I/O, compression, cryptography and sorting, plus a large cache hierarchy topping out near 3.5 GB of virtual L4 cache. IBM hasn't named the chip or its host system but expects it around 2028, likely powering a future z18-class mainframe.
At Hot Chips 2026, SK hynix's Jaesik Lee said hybrid bonding won't be ready in time for HBM4E and will instead debut with HBM5, as current HBM4 packages are already constrained by a 775-micron thickness ceiling matching standard logic wafers. To keep scaling within that limit, 16-Hi HBM4 stacks now use dies thinned to about 50 microns with half the interlayer gap of 12-Hi designs, while SK hynix continues using its existing MR-MUF bonding method through upcoming Nvidia Rubin-generation products.