GoKawiilRTX 4090 teardown traces how STG.E writes results back to memory
A technical deep-dive follows the STG.E instruction—the global memory store operation in a simple vector-add CUDA kernel—through an RTX 4090's pipeline, from register read through the load/store unit, coalescer, L1 cache, crossbar, and L2 slice, down to DRAM. The author benchmarks how frequently a single warp can issue store instructions, finding a new STG.E can be pushed through the register file, LSU, and coalescer roughly every 6.1 cycles (about 2.3 nanoseconds at 2.6 GHz).