GoKawiil
Tech News
Technical analysis of AMD's upcoming Zen 6 CPU core shows it builds on Zen 5 with expanded out-of-order execution structures while reworking integer scheduler layout and branch prediction recovery logic. Testing indicates Zen 6 reduces the latency penalty of branch mispredictions to roughly 3-3.5ns, down from Zen 5's 3.5-4ns, and improves dual-branch-per-cycle handling within the L1 instruction cache.
AMD's upcoming EPYC 'Venice' server processors, the first to use the Zen 6 architecture, have been benchmarked ahead of release. Built on TSMC's N2P node, Zen 6 introduces a redesigned vector engine with native FP16 support, split integer schedulers, dual I/O dies enabling 16 memory channels, and larger core-dense CCDs scaling up to 32 cores with quadrupled L3 cache. In testing, a 256-core, 1,024-thread EPYC 9996 outperformed the previous-generation 768-thread EPYC 9965 by 93% in SPEC CPU 2026 benchmarks.