PJ5 TTL CPU
Well, we did it… we cracked 4MIPS on our TTL CPU. I have to admit I’m both relieved and surprised. The key parts to achieving this was to decrease the latency for the instruction decode and also the flag register writing. The time to decode an instruction, perform a bit of math and then write to the flags was at around 270nS. With the changes we made, the instruction decode had a radical reworking and the flag writing had some big changes as well, means we go this down to under 200nS. Which m