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Transistors on a roll: 3D circuits built from stacks of flexible membranes

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Why This Matters

The development of 3D stacked silicon nanomembrane transistors represents a significant advancement in overcoming the physical limits of transistor miniaturization, enabling more compact and efficient electronic devices. This innovative stacking method, which uses flexible membranes and a simple roller process, could lead to higher performance chips with reduced manufacturing complexity, impacting both the industry and consumers. As the industry moves toward 3D architectures, these breakthroughs could pave the way for more powerful, energy-efficient electronics in the future.

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NEWS AND VIEWS

27 May 2026 Transistors on a roll: 3D circuits built from stacks of flexible membranes Stacks of transistors built from nanomembranes that can be rolled onto a substrate have been used to fabricate 3D circuits. By Veeresh Deshpande ORCID: http://orcid.org/0000-0002-0349-4857 0 Veeresh Deshpande Veeresh Deshpande is in the Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India. View author publications PubMed Google Scholar

As the electronics industry approaches the physical limit of transistor miniaturization, there is an ongoing shift towards a ‘skyscraper’ model in which transistors are stacked in layers on a single chip. Many unconventional materials have been explored for these 3D circuits, but none can yet compete with silicon, which remains the industry standard for high-performance 2D chips. Writing in Nature, Lam et al.1 report the creation of 3D transistor circuits constructed from stacked silicon nanomembranes. These flexible membranes are peeled off a substrate and stacked onto to the chip using a roller — a simple process that does not require high temperatures but achieves the high silicon-crystal quality that integrated circuits require.

doi: https://doi.org/10.1038/d41586-026-01413-y

References Lam, B. et al. Nature https://doi.org/10.1038/s41586-026-10496-6 (2025). Subramanian, S. et al. IEEE Symp. VLSI Technology https://doi.org/10.1109/VLSITechnology18217.2020.9265073 (2020). Liao, S. et al. IEEE Int. Electron Devices Meet. https://doi.org/10.1109/IEDM45741.2023.10413672 (2023). Radosavljević, M. et al. IEEE Int. Electron Devices Meet. https://doi.org/10.1109/IEDM45741.2023.10413678 (2023). Ha, D. et al. IEEE Symp. VLSI Technol. Circuits https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074874 (2025). Datta, S. et al. IEEE Micro 39, 8–15 (2019). Bishop, M. D., Wong, H.-S. P., Mitra, S. & Shulaker, M. M. IEEE Micro 39, 16–27 (2019). Jayachandran, D., Sakib, N. U. & Das, S. Nature Rev. Electr. Eng. 1, 300–316 (2024). Download references

Competing Interests The author declares no competing interests.

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