GoKawiilFursoy Slice-1: open-source out-of-order RISC-V core boots Linux 6.6
A developer released Fursoy Slice-1, a clean-slate 2-wide out-of-order superscalar RISC-V processor core written in SystemVerilog, implementing RV64IMAFDV plus Zba, Zbb, Zicsr and Zifencei extensions. The design supports Sv39 virtual memory and machine/supervisor/user privilege modes, has been synthesized to 500 MHz on Nangate 45nm standard cells, and boots mainline Linux 6.6.50 with a BusyBox userspace.
GoKawiil's interpretation of the reporting above, not reported fact.
A functioning out-of-order RISC-V core with full privilege separation and virtual memory support, released openly, could give hobbyists and researchers a reference design for studying advanced CPU microarchitecture without relying on proprietary IP. It also adds to a growing body of community RISC-V silicon projects that demonstrate the architecture scaling beyond simple in-order implementations toward designs comparable to commercial application processors.
- Implements RV64IMAFDV plus Zba, Zbb, Zicsr, Zifencei extensions with 2-wide out-of-order execution.
- Includes a 128-entry reorder buffer, 160-entry physical register file, and Sv39 demand-paged virtual memory.
- Synthesized at 500 MHz on Nangate 45nm cells and verified by booting Linux 6.6.50 with BusyBox.
Digilent Arty A7 FPGA Board — If you're inspired by this out-of-order RISC-V core, the Arty A7 is a fantastic Artix-7 FPGA board for synthesizing and testing your own SystemVerilog CPU designs. It has the capacity and I/O needed to experiment with pipelines, caches, and even boot custom Linux builds on soft cores.
See Digilent Arty A7 FPGA Board on Amazon → Affiliate link — we may earn a commission on purchases, at no extra cost to you. Product picked by AI based on this article; it is not a tested recommendation.Source: github.com, 2026-11-14
Published there as: “Show HN: Fursoy – Out-of-order RV64IMAFDV core in SystemVerilog (Linux 6.6)”
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