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Gate All Around

2 GoKawiil briefs on this topic

IMECAS demonstrates working GAA transistors using DUV lithography, no EUV

China's Institute of Microelectronics (IMECAS) says it has completed early process integration for stacked-nanosheet gate-all-around transistors built entirely with immersion DUV lithography, avoiding EUV tools that Chinese fabs cannot access. The devices reportedly achieved Ion/Ioff ratios above the 5×10⁵ threshold needed to prove effective gate control over the nanosheet stack. However, IMECAS has not released key figures like gate pitch, transistor density, or nanosheet dimensions needed to compare it to actual 3nm-class chips from TSMC or Samsung.

TSMC to adopt High-NA EUV lithography for volume production in 2030

TSMC has confirmed plans to bring High-NA EUV lithography, using 0.55 numerical aperture optics, into high-volume manufacturing by 2030, likely for its A10 or A11 nodes. The company plans to use standard 6x6-inch photomasks initially, followed by a pilot line for larger 6x12-inch photomasks in 2031, aiming for full production with those masks by 2033.