Published on: 2025-06-11 22:35:07
LFSR CPU running Forth Author: Richard James Howe License: 0BSD / Public Domain Email: mailto:[email protected] Repo: https://github.com/howerj/lfsr-vhdl This project contains a CPU written in VHDL for an FPGA using a Linear Feedback Shift Register (LFSR) instead of a Program Counter, this was sometimes done to save space as a LFSR requires fewer gates than an adder, however on an FPGA it will make very little difference as the units that make an FPGA (Slices/Configurable Logic Blocks)
Keywords: bit bits cpu instruction lfsr
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